Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 10, which contains five terminals, is shown in FIG. 1. Memory cell 10 comprises semiconductor substrate 12 of a first conductivity type, such as P type. Substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of substrate 12. Between the first region 14 and the second region 16 is channel region 18. Bit line BL 20 is connected to the second region 16. Word line WL 22 is positioned above a first portion of the channel region 18 and is insulated therefrom. Word line 22 has little or no overlap with the second region 16. Floating gate FG 24 is over another portion of channel region 18. Floating gate 24 is insulated therefrom, and is adjacent to word line 22. Floating gate 24 is also adjacent to the first region 14. Floating gate 24 may overlap the first region 14 to provide coupling from the first region 14 into floating gate 24. Coupling gate CG (also known as control gate) 26 is over floating gate 24 and is insulated therefrom. Erase gate EG 28 is over the first region 14 and is adjacent to floating gate 24 and coupling gate 26 and is insulated therefrom. The top corner of floating gate 24 may point toward the inside corner of the T-shaped erase gate 28 to enhance erase efficiency. Erase gate 28 is also insulated from the first region 14. Memory cell 10 is more particularly described in U.S. Pat. No. 7,868,375, whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. Memory cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on erase gate 28 with other terminals equal to zero volts. Electrons tunnel from floating gate 24 into erase gate 28 causing floating gate 24 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state.
Memory cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on coupling gate 26, a high voltage on source line 14, a medium voltage on erase gate 28, and a programming current on bit line 20. A portion of electrons flowing across the gap between word line 22 and floating gate 24 acquire enough energy to inject into floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in a read condition. The resulting cell programmed state is known as ‘0’ state.
Memory cell 10 is read in a Current Sensing Mode as following: A bias voltage is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias or zero voltage is applied on erase gate 28, and a ground is applied on source line 14. There exists a cell current flowing from bit line 20 to source line 14 for an erased state and there is insignificant or zero cell current flow from the bit line 20 to the source line 14 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Current Sensing Mode, in which bit line 20 is grounded and a bias voltage is applied on source line 24. In this mode the current reverses the direction from source line 14 to bitline 20.
Memory cell 10 alternatively can be read in a Voltage Sensing Mode as following: A bias current (to ground) is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias voltage is applied on erase gate 28, and a bias voltage is applied on source line 14. There exists a cell output voltage (significantly >0V) on bit line 20 for an erased state and there is insignificant or close to zero output voltage on bit line 20 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Voltage Sensing Mode, in which bit line 20 is biased at a bias voltage and a bias current (to ground) is applied on source line 14. In this mode, memory cell 10 output voltage is on the source line 14 instead of on the bit line 20.
In the prior art, various combinations of positive or zero voltages were applied to word line 22, coupling gate 26, and floating gate 24 to perform read, program, and erase operations
In response to the read, erase or program command, the logic circuit 245 (in FIG. 2) causes the various voltages to be supplied in a timely and least disturb manner to the various portions of both the selected memory cell 10 and the unselected memory cells 10.
For the selected and unselected memory cell 10, the voltage and current applied are as follows. As used hereinafter, the following abbreviations are used: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG).
TABLE NO. 1PEO (Positive Erase Operation) TableWL-BL-CG-unselCG-EG-WLunselBLunselCGsame sectorunselEGunselRead1.0-2 V  0 V0.6-2 V0 V/FLT 0-2.6 V0-2.6 V0-2.6 V0-2.6 V0-2.6 VErase0 V0 V  0 V0 V   0 V0-2.6 V0-2.6 V11.5-12 V 0-2.6 VProgram1 V0 V  1 uAVinh10-11 V0-2.6 V0-2.6 V4.5-5 V0-2.6 VSLSL-unselRead0 V0 V/Bias/FLTErase0 V0 VProgram4.5-5 V  0-1 V/FLT
In a recent application by the applicant—U.S. patent application Ser. No. 14/602,262, filed on Jan. 21, 2015, which is incorporated by reference—the applicant disclosed an invention whereby negative voltages could be applied to word line 22 and/or coupling gate 26 during read, program, and/or erase operations. In this embodiment, the voltage and current applied to the selected and unselected memory cell 10, are as follows.
TABLE NO. 2PEO (Positive Erase Operation) TableWL-BL-CG-unselCG-EG-WLunselBLunselCGsame sectorunselEGunselRead1.0-2 V  −0.5 V/0 V0.6-2 V0 V/FLT 0-2.6 V0-2.6 V0-2.6 V0-2.6 V0-2.6 VErase0 V0 V  0 V0 V   0 V0-2.6 V0-2.6 V11.5-12 V 0-2.6 VProgram1 V−0.5 V/0 V  1 uAVinh10-11 V0-2.6 V0-2.6 V4.5-5 V0-2.6 VSLSL-unselRead0 V0 V/Bias/FLTErase0 V0 VProgram4.5-5 V  0-1 V/FLT
In another embodiment of U.S. patent application Ser. No. 14/602,262, negative voltages can be applied to word line 22 when memory cell 10 is unselected during read, erase, and program operations, and negative voltages can be applied to coupling gate 26 during an erase operation, such that the following voltages are applied:
TABLE NO. 3PNEO (Positive Negative Erase Operation) TableWL-BL-CG-unselCG-EG-WLunselBLunselCGsame sectorunselEGunselRead1.0-2 V  −0.5 V/0 V0.6-2 V0 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V  0-2.6 VErase0 V−0.5 V/0 V  0 V0 V−(5-9) V  0-2.6 V0-2.6 V8-9 V0-2.6 VProgram1 V−0.5 V/0 V  1 uAVinh 8-9 VCGINH (4-6 V)0-2.6 V8-9 V0-2.6 VSLSL-unselRead0 V0 V/Bias/FLTErase0 V0 VProgram4.5-5 V  0-1 V/FLT
In the above table, “FLT” refers to a floating node.
The CGINH signal listed above is an inhibit signal that is applied to the coupling gate 26 of an unselected cell that shares an erase gate 28 with a selected cell.
In the prior art systems described above, during a read or programming operation, a single row and a single column would be activated, such that the flash memory cells located at the selected row and selected column could be read from or programmed.
With flash memory systems becoming ubiquitous in all manner of computing and electronic devices, it is increasingly important to create designs that enable faster read and programming operations. What is needed is flash memory system that allows a greater number of flash memory cells to be accessed for read and programming operations compared to the prior art systems.